AI has an uncontrollable lust for hardware power. But at TSMC’s annual Open Innovation Platform (OIP) in Amsterdam, low power consumption and fast design iterations actually reign supreme. AI problems are in fact being solved with AI solutions.
It has been clear for some time that Moore’s Law isn’t holding up well. Whereas previously the ever tighter and tighter placement of transistors was enough for stunning performance gains, players in this industry must find improvements in more exotic ways. This is driving TSMC to place an even stronger emphasis than before on efficiency, which can only be achieved with close collaboration and, yes, AI.
AI to design faster
TSMC itself compares the chip industry to the Olympics during the presentation. “Only the best win in the Open Innovation Platform (OIP) arena,” one of the company’s representatives stated. Those not innovating fast enough or smart enough will lose out to the white-hot competition. This is a somewhat strange comparison, if we’re being honest. After all, the chip industry relies on collaborative efforts more than most. In fact, TSMC, along with Belgium’s imec and others, relies on mutual support and interoperability. For example, TSMC’s OIP (both the name of the open platform and the annual event) contains 70,000 IP blocks, effectively a giant box of concepts to manufacture chips.
These blocks are very widely applicable, as the movement toward 3D-stacked chips shows. Together with EDA partners, which are the developers of chip design programs, it has been working on 3Dblox for this purpose. This is a programming language to create an interoperable design so that all partners in the semiconductor world are spared some ugly translation efforts and can benefit from each other’s progression. This is especially important for a three-dimensional design with very tight tolerances, where one error can ruin a hugely complex building process.
An example of one of the ‘hacks’ required here: a chimney design within a chip that uses stacking. Stacking, as you might have already guessed, refers to the stacking of chips. But these somehow need to get rid of their heat or they will inevitably perish. Normally this heat transfer takes place via the IHS (Integrated Heat Spreader), but a stacked design inherently contains an extra chip sitting atop another. During one of the sessions of TSMC’s OIP, there’s mention of a so-called “dummy chimney via stack” right above the hotspot of the underlying chip. Such an exotic move is necessary for the third dimension to provide further acceleration.
EDA (Electronic Design Automation) is also highlighted prominently during OIP, i.e. the design stage pre-production. This is an area where AI comes in handy in many ways. LLMs, for example, create summaries for design docs, while Reinforcement Learning detects errors in multiple design phases and optimizes wherever possible. Dan Kochpatcharin, Head of Ecosystem & Alliance Management Division at TSMC, cites that AI in all its forms can provide as much as 60 percent speed improvements to the design process.
Shifting market
Such benefits apply to every chip designer, from Nvidia to a smart doorbell specialist. After all, those who finish the design earlier can ask TSMC to bake chips sooner. Those who rely on the most advanced processes (aka nodes), however, face competition. Apple leads the way as an early adopter, with Nvidia, AMD and Intel regularly in its wake. TSMC is also perfectly on track in terms of its roadmap for the next few years, so it’s pretty plain sailing for the high-end. AI accelerators and iPhone SoCs will keep coming at a steady pace, benefiting from the latest nodes.
Meanwhile, another industry is moving into the newer nodes. The automotive world, long content with old familiar processes for their chip components, is innovating. Jan Philipp Gehrmann, VP of Marketing at NXP, says the innovation time for automotive chips has moved from 5 years to 2 years. The automotive chip supply chain, once haphazard and decentralized, has also consolidated thanks to car manufacturers paying more attention to it. Before, they regularly had very little regard for what digital components were being used by suppliers to later put into a brake system, ECU or seat heater.
But now that has changed. The Software-Defined Car is on the rise, Gehrmann says, with higher requirements for onboard hardware. Cars must be able to make full use of all their sensors and eventually drive themselves. That requires computing power and oversight, which a party like NXP is assisting automakers with. TSMC makes NXP products based on everything from 90 nanometer to 5 nanometer nodes, or, to put it another way, it’s using older chip processes that are 20 years old as well as relatively new ones that are 4 years old.
The collaboration between NXP and TSMC goes deeper than that of just a customer and provider, Gehrmann said. Specifically, it revolves around ESMC (the joint venture of TSMC, NXP, Bosch and Infineon for chip manufacturing within Europe) and VSMC (with NXP and VIS, a TSMC spin-off). Through these partnerships, NXP products are manufactured in multiple locations, with all the geopolitical security that brings.
Profit with little
Kochpatcharin of TSMC obviously pays close attention to the bleeding edge at the Taiwanese company. For example, he says backside power delivery is best achieved through TSMC manufacturing (and not at Intel, for example), a technology that for now applies only to the very fastest and very latest products. Also, designs are getting bigger by sticking chiplets together. This is what Nvidia Blackwell partly owes its gigantic performance leap to compared to Hopper.
But this distracts from the gains still achievable with older chip nodes. We spoke to Innatera, a Dutch chip company that emerged from the Technical University of Delft. TSMC was already working with the collective behind what’s now Innatera at an academic level. Innatera wants to make much more efficient chips than before in certain edge applications. Consider presence detection in an office, voice recognition or health measurements. Using the older 28 nanometer process (TSMC has been offering this since 2011), Innatera says a radically different design, inspired by the structure of brains, allows a performance gain of 10,000 times. In short, there is still a huge amount of gains to be made on older chip processes, more than one might expect.
This makes TSMC’s position clear. Not only is the absolute top of the market tied to the Taiwanese player (Nvidia, Apple, even competitor Intel) thanks to proven performance, but it also has close ties with companies just starting out focusing on efficiency at ultra-low power. This is because it works closely with the entire value chain, from EDA to start-ups. And right from academia as well, where practically every engineer starts in this industry. When TSMC calls on the chip world to be more efficient, it does so by being involved in the matter on all levels. It is working together to achieve its stated goal, which will increasingly be about optimization and efficiency rather than pure performance.
Also read: TSMC is in better shape than ever, despite fierce competition