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Intel is currently receiving all High-NA EUV machines from ASML, putting it one step ahead of competing chip makers. According to TSMC, however, there is nothing to worry about: the next chip processes will arrive on time and don’t need the brand new tech.

That’s according to Kevin Zhang, SVP Business Development & Overseas Operations Office at TSMC. He made this observation during the TSMC Technology Symposium in Amsterdam. The company wants to see firm evidence of High-NA’s real-world effectiveness before it’s taking the plunge. It’s also not a fan of the steep price, which is said to amount to 350 million euros a piece.

It underscores the importance of the predictability that TSMC strives for above all else. Partners must be able to rely on TSMC delivering according to its stated roadmaps, something that has long been a thorny issue at Intel, for example. The role as a stable element in the chip industry is something TSMC continuously emphasized during the Amsterdam event. Therefore, a rushed introduction of High-NA EUV evidently isn’t a good fit.

Currently, the Taiwanese chipmaker produces products on a 3 nanometer node, which is a loose reference to the scale at which a chip is baked. The iPhone 15 series was built using this “N3” node in TSMC’s parlance, but nothing else has yet emerged that uses it. Later manufacturing processes will bear the name Angström, the measurement unit one order of magnitude below nanometers. 16 Angström (A16) will see the light of day in 2027, and, according to Zhang, it doesn’t need ASML’s High-NA EUV machine to surface. This equipment is considered the state of the art for modern chips and is currently still in the testing phase. Mass production should be possible in about two years.

Efficiency by reversing power supply

High-NA is a further development of EUV lithography, which uses extreme ultraviolet light to draw chip designs on the silicon wafer. Zhang is confident that years of expertise with EUV will continue to be of great benefit to TSMC. “The driver’s experience is just as important as the performance of the car,” Zhang states. With optimizations developed in-house, TSMC has consistently produced more viable chips per wafer as time has gone on.

TSMC is also optimistic about future chip processes. “There is no showstopper [for the A16 process, ed.] so far,” Zhang said. With this manufacturing process, the company expects to make a big efficiency leap, mostly because of “Super Power Rail” (SPR), a way to power chips from the back instead of the front side. Previously, electricity was only powered from the front-facing side of a processor, but both Intel and TSMC are changing this paradigm.

At Intel this is called “PowerVia,” at TSMC it is called SPR. Although the aim is the same, their implementations differ. Regardless, both techniques let transistors get their power more directly than before and prevent a chip’s copper circuits from being the main limiting factor for performance. However, it does come with its heat challenges. Thermals generated by supplying power from the top of the chip is easier to remove, as it sits directly underneath an integrated heat sink that itself gets cooled by air or liquid cooling.

European chip factory

Also at the event, TSMC brought news of the chip factory to be built in Dresden, Germany. Construction will begin in the fourth quarter of 2024. When asked, Zhang would not reveal whether there are plans for further expansion in Europe. Currently, chips from Dresden will be baked only on the older 16nm and 12nm processes. The plant is a joint venture of TSMC with NXP, Infineon and Bosch. The latter three each own 10 percent of the newly formed ESMC (European Semiconductor Manufacturing Company). Those parties are not guaranteed products from the plant, however, according to Zhang: TSMC is the principal owner and is letting the customer base develop organically.

Also read: BE Semiconductor closes lucrative chip deal with (presumably) Intel