On Thursday, Cisco Systems updated its family of Silicon One semiconductors used in next-gen 5G network routers and switches. The new releases will have a high-end chip design to enable “web-scale” switching, breaking new ground in speeds while also boasting an industry-leading maximum bandwidth of 25.6 terabytes per second.
The Silicon One chip made its debut in December 2019.
At the time, the company said that the aim was to create a common foundation for future networks. The Silico One processors are used to build fixed and modular routers and switches in vast networks used by enterprises and telecom companies.
Traditionally, the networks were made up of thousands of different devices, powered by a variety of application-specific integrated circuits, causing fragmentation and creating problems. In those systems, the code has to be validated separately for each device type.
Cisco is trying to fix this problem with the Silicon One family, which brings capabilities that can power all types of networking devices, to remove challenges caused by using a variety of chips with unique architectures.
The Thursday launch brought three new Silicon One processors to the family, to bring the total chip count to 10, since the 2019 debut.
The three new entrants include the Cisco Silicon One G100 processor, which is the first programmable and fully shared packet buffered device to hit 25.6Tbps. it was built using a seven-nanometer chip manufacturing process.
Eyal Dagan, the senior Veep of the Common Hardware Group at the company, said that the extension of the Cisco Silicon One Family to 25.6Tbps provides the higher performance routing silicon.
It has 1.7 times higher bandwidth and more than three times higher packet-per-second.