Siemens Digital Industries Software, a division of Siemens AG, announced the release of ‘Tessent Multi-die’. The technology simplifies the design process for testing chips built with advanced packaging.
Traditionally, chips have been packaged with a single silicon tile inside. Now, as the industry struggles to condense more and more computational power into these tiles, companies like Intel have begun stacking several of them, occasionally mixing and matching various technologies to boost performance. Because of the numerous layers of tiles, testing these chips has become increasingly difficult.
Making advanced-packaged chip testing accessible
Testing is an essential element of the chip-making process, and a connection for testing must be incorporated into the chip before it is manufactured. To deal with the issue of complexity in testing, Siemens has had to work with clients on a case-by-case basis until recently, Siemens Tennent GM Ankur Gupta told Reuters.
The executive announced that Siemens is now leveraging all of the knowledge and experience it accumulated to automate the process, creating a general-purpose testing solution for advanced chips that is available for everyone to utilize.
Tessent Multi-die
The technology, ‘Tessent Multi-die’, can create die-to-die connection designs and allow package-level tests using the Boundary Scan Description Language, in addition to providing an extensive test for 2.5D and 3D IC designs (BSDL).
Tessent Multi-die also incorporates flexible parallel port (FPP) technology using Siemens’ Tessent TestKompress Streaming Scan Network software’s packetized data transport capabilities.
Tessent TestKompress Streaming Scan Network was introduced two years ago and decouples core-level design for testability (DFT) needs from chip-level test delivery resources. This allows for a no-compromise, bottom-up DFT approach, significantly simplifying DFT design and execution while cutting test time by up to 400 percent.
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