The sixth-generation EPYC server processors are now available. Codenamed Venice, the new Zen 6 chip architecture delivers a significant performance boost for EPYC chips, with a focus on agentic AI workloads. The processors will be shipped shortly and will be available on platforms such as Microsoft Azure and Oracle Cloud Infrastructure.
Systems featuring the new SP7 processors have been shipping from major OEMs and ODMs since Tuesday, AMD reports. The chips were first announced in July during AMD’s Advancing AI event. Meta is a so-called “lead customer.” It is validating the new EPYC systems for a large-scale rollout. The company led by CEO Mark Zuckerberg signed a multi-year deal with AMD in February for up to 6 gigawatts of Instinct GPUs. The first gigawatt of those runs on Venice CPUs.
The CPU is back in the spotlight
According to AMD, the fifth generation, Turin, was adopted faster than any previous EPYC generation. Venice is set to continue that trend, but with a distinctly different focus. AI significantly expands the role of the CPU “at every layer of the data center,” according to Dan McNamara, SVP and general manager of Compute and Enterprise AI at AMD.
We’ve noted before that the CPU is back in the spotlight now that AI infrastructure is placing demands on systems far beyond the GPU. A single agent-based workflow frequently turns to the CPU for critical tasks. It calls up models, retrieves data, executes code, and communicates with existing databases and applications. Incidentally, much of that work never reaches the GPU at all. An often-overlooked reality of AI workloads is that every tool call and other interruption effectively restarts the workload within the GPU. Only the surrounding IT applications and infrastructure reveal the impact of the AI actions, with the CPU acting as the conductor of all tasks except inference. AMD identifies three roles for the central processor that are relevant here. First, general-purpose services, the classic workloads. These have now been expanded to include host nodes, which supply data to GPUs. Next is the role of the sandbox in which agents run, with all the security implications that entails. Venice offers a dedicated variant for each of these roles.
256 cores, 2 nanometers, and PCIe 6.0
The top-of-the-line model, the EPYC 9996, features 256 Zen 6c cores and 512 threads and is manufactured using TSMC’s 2-nanometer process. It utilizes 16 memory channels, delivering approximately 1.6 TB/s of bandwidth with high-speed MRDIMMs, plus 128 PCIe 6.0 lanes with CXL 3.1 and 1,024 MB of L3 cache. With a suggested retail price of $14,904, the chip costs about the same as its predecessor, the EPYC 9965, but offers 64 more cores. Those looking specifically for high clock speeds can opt for the standard Zen 6 models. Those have up to 96 cores and reach up to 5.3 GHz. It depends on where the bottleneck lies, but for AI, bandwidth is usually the limiting factor.
Interestingly, AMD no longer refers to TDP. Instead, it uses the term “Default CPU Power,” which reflects the combined power consumption of the compute and I/O dies. For the 9996, that’s 600 watts, though the chip can also be configured to run at 400 watts.
Independent tests show that the generational leap is significant, though not equally so across the board. In Tom’s Hardware’s benchmarks, a dual-socket 9996 system performs up to 93 (!) percent better than a dual-socket EPYC 9965 in the SPEC CPU 2026 integer throughput test. For Java and database workloads, the gain is much more modest at around 24 percent; for rendering in Blender, it ranges between 30 and 40 percent. The most commonly reported IPC gain is in the 20–25 percent range, a substantial advantage historically speaking between generations.
Bold claims, fine print
AMD claims that a system with the EPYC 9996 is up to 3.7 times faster than a system with Nvidia Vera, as measured by SPECrate2017_int_base. Compared to the Intel Xeon 6980P, it is said to deliver up to 2.2 times the performance and twice the performance per dollar.
There are two caveats here. The Vera score is merely an estimate by AMD itself, based on previous tests by Phoronix. And the Xeon 6980P is Intel’s top-of-the-line model from 2024. According to AMD’s own footnotes, the performance lead over the newer Xeon 6990E+ is approximately 1.8 times. That comparison with the older product may be of interest to those considering a switch.
For agent sandboxes, AMD claims approximately 3.3 times as many agents per CPU watt as Vera, and 2.5 times as many as the Xeon 6980P. Again, this is a theoretical calculation. AMD uses the number of available threads as a measure of the number of agents and bases its calculations on a 256-core chip set to 400 watts. How many agents can actually fit on a server depends heavily on the model, memory, and software. This also assumes full utilization, which is unlikely to be common in practice. The high-clock-frequency host-node CPUs are said to achieve up to 1.8 times as much LLM output as the previous generation. That figure is, once again, a projection.
From server to rack
Venice will also be integrated into the Helion racks that AMD unveiled in October at the OCP Global Summit. This is an open blueprint for a server configuration that AMD describes as a new type of agentic AI infrastructure. It is notably more cost-effective than a primarily GPU-driven architecture, as the CPU takes center stage here, while the GPU is optional. There are three variants. First is Helion Liquid, designed to be deployed alongside AMD’s Helios GPU racks for maximum “agent density.” Next is Helion Air, which is suitable for existing air-cooled data centers. Finally, there is Helion Air Inference, which combines CPUs and GPUs for local inference within a single rack. Some configurations reach a staggering 73,728 threads per rack.
Microsoft has made the EPYC Zen 6-based Azure HDv2 available in preview. It is designed for data processing for agentic AI and “conventional” HPC workloads. Each VM features more than 500 physical Zen 6 cores and 3.8 TB of DDR5 memory. In addition, Azure HXv2 will be introduced for EDA (electronic design automation) and technical computations, and ND MI455X v7 for AI inference at scale. The latter is based on the well-known Helios, the rack platform that Azure has previously adopted, and is considered a direct alternative to Nvidia’s Vera Rubin rack-scale system. Meanwhile, Oracle is running its OCI Compute E7 instances on Venice. These are intended for general-purpose enterprise applications and CPU services related to AI models.
But the Venice family isn’t complete yet. Processors for the smaller SP8 socket will follow in the first half of 2027, and the Venice-X variants with 3D V-Cache for HPC will arrive in the second half of that year.