The new technology will deliver a “huge power and efficiency boost”, the company says.
Graphcore this week introduced a new artificial intelligence (AI) processor, called the Bow IPU. The new chip uses an innovation called wafer-on-wafer technology to speed up calculations.
Graphcore is a UK-based startup backed by more than $680 million in venture funding. In recent years, the company has shipped tens of thousands of AI processors to customers such as cloud providers and research institutions.
Graphcore’s new Bow IPU processor can manage up to 350 trillion processing operations per second, the company claims. The Bow is an improved version of an existing Graphcore chip called the Colossus Mk2. Its IPU features the same number of processing cores as the Colossus Mk2. It also has an identical amount of memory. But it provides up to 40% more performance thanks to the fact that it’s based on a new wafer-on-wafer design.
Introducing “The Wow Factor”
Nigel Toon and Simon Knowles, Graphcore’s CEO and CTO, announced the Bow IPU in a blog post. “Bow Pods are all about delivering real-world performance, at scale, for a wide range of AI applications,” they write. These include everything from GPT and BERT for natural language processing to EfficientNet and ResNet for computer vision. They also serve graph neural networks and many more.
In addition to up to 40% performance gains, Bow Pod systems are also significantly more power efficient than their predecessors. Tested across a range of real world applications, Bow Pods show an improved performance-per-Watt of up to 16%.
“Our Bow Pod systems deliver this giant performance boost and improved power efficiency thanks to the use of a world first in 3D semiconductor technology in the new Bow IPU processor,” they explain.
“We are proud to be the first customer to market with TSMC’s Wafer-on-Wafer 3D technology, which we have developed in close partnership with them. Wafer-on-Wafer has the potential to deliver much higher bandwidth between silicon die and is being used to optimise power efficiency and improve power delivery to our Colossus architecture at the wafer level.”