Marvell has announced the Teralynx T100, a new network switch chip for AI data centers. The chip offers a throughput capacity of 102.4 Tbps and is designed for networks that connect large clusters of GPUs and other AI accelerators.
The launch comes at a time when the scale of AI clusters is growing rapidly. Training environments increasingly consist of thousands to tens of thousands of accelerators, placing greater demands on the underlying network layer. Not only does bandwidth play a role here, but also latency, power consumption, and the ability to efficiently interconnect large numbers of systems.
The launch reflects a broader shift within AI infrastructure. While attention has long focused primarily on GPUs and AI accelerators, the network layer is becoming increasingly important. In large AI clusters, tens of thousands of systems must continuously exchange data. As a result, latency, power consumption, and the scalability of switches are becoming increasingly critical to the performance of an AI data center.
According to Marvell, the T100 consumes less than 1,000 watts, making its energy consumption lower than that of competing products in the same category. This is relevant for data centers where total power consumption continues to rise. Modern GPU racks are now approaching power levels of approximately 120 kW, while network components, according to the company, account for 15 to 25 percent of a rack’s total power consumption.
Fewer network layers
The Teralynx T100 supports configurations with up to 512 ports. According to Marvell, this allows operators to build larger networks with fewer intermediate links. Fewer network layers can reduce latency and cut down on the number of optical connections required.
The chip is manufactured using a 3-nanometer process and designed as a single integrated silicon design. According to Marvell, this enables a different approach compared to switches originally developed for traditional enterprise or cloud environments and later adapted for AI applications. The company also states that the architecture is optimized for predictable performance in large-scale AI environments, where delays in one part of the network can impact the performance of an entire training environment.
In addition to traditional Ethernet environments, Marvell is explicitly focusing on new network architectures for AI. The T100 supports, among other things, Ethernet Scale-Up Networking (ESUN) and complies with specifications from the Ultra Ethernet Consortium. As a result, the chip can be deployed in both so-called scale-out networks, where large numbers of systems are interconnected, and scale-up architectures within individual AI systems.
Marvell offers the T100 in various packaging options, including versions with integrated copper or optical interfaces. This is intended to give hyperscalers and cloud providers greater flexibility in designing their network architecture.
Competition in AI networks is intensifying
The introduction of the T100 underscores the growing importance of network technology within AI infrastructure. While attention in recent years has primarily focused on GPUs from companies like NVIDIA and AI accelerators from AMD and others, competition in the network layer is also growing.
For AI infrastructure providers, network efficiency is becoming increasingly important as clusters grow larger. Delays in communication between accelerators can limit the performance of training and inference workloads, while the energy consumption of network equipment is becoming an increasingly significant factor in the total cost of ownership of AI data centers.
Marvell expects to begin shipping the first units of the Teralynx T100 to customers this quarter.