Intel unveils its multi-chiplet Sapphire Rapids CPU with HBM

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Intel confirmed that the 4th Generation Xeon Scalable ‘Sapphire Rapids’ processors will have on-package HBM memory in late 2020. However, the company has never demonstrated an actual CPU equipped with HBM or given details of the DRAM configuration.

The company finally showcased the processor with HBM at the International Symposium on Microelectronics hosted by IMAPS earlier this week, confirming its multi-chiplet design.

Intel confirmed several times that the Sapphire Rapids processors will support HBM and presumably HBM2E and DDR5 memory while having the ability to use HBM with or without main DDR5 memory. It was only this week that it showed HBM-equipped CPU.

Adequate data transfer rate

Each of the four Sapphire Rapids chiplets has two HBM memory stacks using two 1024-bit interfaces (a 2048-bit memory bus). The formal information says that JEDEC’s HBM2E specifications reach a 3.2 GT/s  data transfer rate.

However, last year, SK Hynix started mass producing the 16GB 1024-pin known-good stacked dies (KGSDs) rated for a 3.6 GT/s operation.

If Intel goes with the KGSDs, HBM2E memory will give Sapphire Rapids CPU a 3.68 TB/s peak memory bandwidth (921.6 GB/s per die) but only for 128GB of memory.

Differences from the competition

Contrast this offering with SPR’s eight DDR5-4800 memory channels supporting one module per channel and delivering 307.2 GB/s will support at least 4TB of memory using Samsung’s recently announced 512GB DDR5 RDIMM modules.

It is worth noting that the HBM-equipped Sapphire Rapids comes in a large BGA form factor and will be soldered directly onto the motherboard. That is not a surprise, given that the Intel LGA4677 form-factor is narrow and the CPU does not have enough space on its package for HBM stacks.

It seems that the 4th Generation Xeon Scalable will be the first to use Intel’s latest packaging technologies and design paradigm.